1. Field of the Invention
The present invention concerns a MOS type variable capacitance device. Particularly, it relates to a MOS type variable capacitance device which can be manufactured with ease by a general manufacturing process for semiconductor circuit devices and attributes to the improvement of the performance of voltage controlled oscillators and the like.
2. Description of Related Art
An example of circuits using variable capacitance devices includes a voltage controlled oscillation circuit (hereinafter simply referred to as VCO circuit). FIG. 14 shows a VCO circuit 100 as an example. The VCO circuit 100 includes two variable capacitance devices 102. A control voltage VC is applied to a node 104 as a connection point of them. Since a constant voltage is applied in the form of a DC current to a node 105, the capacitance value of the variable capacitance device 102 can be controlled by controlling the control voltage VC. Accordingly, in the VCO circuit 100, an LC resonance frequency for the variable capacitance devices 102 and coils 103 can be controlled by the control voltage VC. It is desirable for the characteristic of the VCO circuit that the obtained oscillation frequency changes linearly for a wide range.
For obtaining the characteristic of the VCO circuit 100, it is necessary to use a variable capacitance device that can obtain the linear change of the capacitance over a wide range relative to the controlled voltage VC.
FIG. 15 shows a plan view schematically showing a MOS type variable capacitance device disclosed in JP-A No. 2000-58877 as a Patent Document 1 and FIG. 16 shows a cross sectional view taken along line A-A′ in FIG. 15. In a MOS type variable capacitance device 200, a first semiconductor layer 202 comprising a p-well is formed within an n-type semiconductor substrate 201 as shown in FIG. 16. On the surface of the first semiconductor layer 202, p-type impurities are diffused selectively to form a second semiconductor layer 203. Further, a contact layer 204 formed by selectively diffusing p-type impurities at high concentration is formed being spaced from the second semiconductor layer 203. Then, on the surface of the second semiconductor layer 203, a gate insulative layer 205 comprising silicon oxide is formed, and a gate electrode 206 is formed on the surface of the gate insulative layer 205.
The second semiconductor layer 203 is constituted with plural regions 203a and 203b (two regions in the drawing) having different flat band voltages. The regions 203a and 203b of different flat band voltages are formed such that the impurity concentration changes stepwise.
The regions 203a and 203b of different flat band voltages constitute capacitances C100 and C200 respectively. Then, the capacitance CT100 of the MOS type variable capacitance device 200 forms a synthesis capacitance of capacitances C100 and C200. The capacitances C100 and C200 are changed by changing the inter-terminal voltage VT between the gate electrode 206 and the contact layer 204 and, accordingly, the capacitance CT100 of the MOS type variable capacitance device 200 changes.
FIG. 17a shows the characteristic of the capacitance change relative to the inter-terminal voltage VT in a case where the flat band voltages for the regions 203a and 203b are VFB and VFB′ respectively. While the respective characteristic curves for the capacitances C100 and C200 shift in parallel in accordance with the difference of the flat band voltages VFB, VFB′ and the voltage value for the inter-terminal voltage VT at which the change of capacitance starts is shifted, profiles of the characteristic curves of the capacitance C100 and C200 per se do not change. Accordingly, the capacitance CT100 of the MOS type variable capacitance device 200 as the synthesis capacitance of them shows a characteristic having a linearity within a range corresponding to the capacitance change regions due to the capacitance C100 and C200 relative to the inter-terminal voltage VT as shown in FIG. 17b. 
However, the prior art described above involves, the following problems. That is, in the MOS type variable capacitance devices 200 disclosed in the Patent Document 1, the linear characteristic of the capacitance CT100 is obtained by the synthesis of the capacitance changes in the two regions of different flat band voltages, for the variable capacitance device 102 required for the VCO circuit 100, a characteristic of wider range and of good linearity to the control voltage VT is sometimes demanded. In the MOS type capacitance device 200, a plurality of regions of flat band voltages different with each other have to be formed. For preparing a plurality of regions, an exposure mask for selectively diffusing impurities is further necessary and, correspondingly, additional steps such as an exposure step and cleaning step are required. The manufacturing steps are complicated and the manufacturing cost increases inevitably to bring about a problem.
The present invention has been achieved in order to solve the problem in the prior art described above. That is, the object is to provide a MOS type variable capacitance device that can obtain a characteristic with a good linearity over a wide range relative to the control voltage VT, and cope with the improvement of the performance of the VCO circuit and the like and, in addition, has a simple structure and can be manufactured easily with no requirement of adding a mask and steps in the general process for manufacturing semiconductor circuit devices.